AI Agent Skills

Integration of the RISC Zero verifiable compute platform with Ethereum and EVM chains.

A graphical processor simulator and assembly editor for the RISC-V ISA

RARS -- RISC-V Assembler and Runtime Simulator

RISC-V Assembler and Runtime Simulator

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Su…

Lightweight inference library for ONNX files, written in C++. It can run Stable Diffusion XL 1.0 on a RPI Zero 2 (or in 298MB of RAM) but also Mistral 7B on desktops and…

SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.

Use when bringing up bare-metal or kernel code on a new architecture, SoC, or board (RISC-V, ARM, x86, ESP32) and it won't boot, hangs after boot, or faults early; cover…

Use when building or debugging a firmware and boot chain (RISC-V SBI, UEFI, ACPI, a bootloader handoff like Limine to an OS) or adding measured boot with a TPM, and a st…