Skill-Verzeichnis
Jede Empfehlung bleibt mit ihrem Repository, Audit und Installationspfad nachvollziehbar.
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
A graphical processor simulator and assembly editor for the RISC-V ISA
Lightweight inference library for ONNX files, written in C++. It can run Stable Diffusion XL 1.0 on a RPI Zero 2 (or in 298MB of RAM) but also Mistral 7B on desktops and servers. ARM, x86, WASM, RISC-V supported. Accelerated by XNNPACK. Python, C# and JS(WASM) bindings available.
SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.
RARS -- RISC-V Assembler and Runtime Simulator
Integration of the RISC Zero verifiable compute platform with Ethereum and EVM chains.
RISC-V Assembler and Runtime Simulator
Skill-Verzeichnis
Jede Empfehlung bleibt mit ihrem Repository, Audit und Installationspfad nachvollziehbar.
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
A graphical processor simulator and assembly editor for the RISC-V ISA
Lightweight inference library for ONNX files, written in C++. It can run Stable Diffusion XL 1.0 on a RPI Zero 2 (or in 298MB of RAM) but also Mistral 7B on desktops and servers. ARM, x86, WASM, RISC-V supported. Accelerated by XNNPACK. Python, C# and JS(WASM) bindings available.
SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.
RARS -- RISC-V Assembler and Runtime Simulator
Integration of the RISC Zero verifiable compute platform with Ethereum and EVM chains.
RISC-V Assembler and Runtime Simulator
Skill-Verzeichnis
Jede Empfehlung bleibt mit ihrem Repository, Audit und Installationspfad nachvollziehbar.
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
A graphical processor simulator and assembly editor for the RISC-V ISA
Lightweight inference library for ONNX files, written in C++. It can run Stable Diffusion XL 1.0 on a RPI Zero 2 (or in 298MB of RAM) but also Mistral 7B on desktops and servers. ARM, x86, WASM, RISC-V supported. Accelerated by XNNPACK. Python, C# and JS(WASM) bindings available.
SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.
RARS -- RISC-V Assembler and Runtime Simulator
Integration of the RISC Zero verifiable compute platform with Ethereum and EVM chains.
RISC-V Assembler and Runtime Simulator
Skill-Verzeichnis
Jede Empfehlung bleibt mit ihrem Repository, Audit und Installationspfad nachvollziehbar.
Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
A graphical processor simulator and assembly editor for the RISC-V ISA
Lightweight inference library for ONNX files, written in C++. It can run Stable Diffusion XL 1.0 on a RPI Zero 2 (or in 298MB of RAM) but also Mistral 7B on desktops and servers. ARM, x86, WASM, RISC-V supported. Accelerated by XNNPACK. Python, C# and JS(WASM) bindings available.
SP1 is a zero‑knowledge virtual machine that proves the correct execution of programs compiled for the RISC-V architecture.
RARS -- RISC-V Assembler and Runtime Simulator
Integration of the RISC Zero verifiable compute platform with Ethereum and EVM chains.
RISC-V Assembler and Runtime Simulator