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readable-verilog-generator
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Generate, analyze, improve, and verify readable Verilog-2001 RTL through the bundled runtime under scripts/python/. Keep design RTL and verification testbenches in .v files, use scripts/python/facade/verilog_api.py for host integration, and treat formatter-AST and external-tool evidence as stronger than model self-assessment.
create/write: confirm the design contract, then use requirements -> codegen_plan -> spec_document -> python -> rtl.
deep_review: insert a non-empty structured review between the Python semantic model and RTL; it must cover interface, reset, timing/pipeline, handshake or FSM behavior, width, synthesis, testbench coverage, and risks.
review/analyze: remain read-only and report the eight public gate states before suggesting changes.
annotate: preserve an immutable normalized baseline, change only // comments, prove token equivalence from that baseline, and rerun the final deliverable gate.
repair/refactor: bind the task to real RTL, reproduce or validate the issue, and apply the smallest evidence-backed change.
agentic_repair: use the existing-RTL verify_existing_verilog(...) loop with an explicit conservative, semi_auto, or auto_apply choice.
validate: collect static or external evidence without implicitly editing RTL.
Load references/workflows/verilog_dispatcher.md before routing. Existing assets, logs, waveform clues, and mixed inputs use its read-only entry decision before any generation, validation, backup, or remote action.
The package root contains install.ps1, install.sh, and install.bat beside this SKILL.md. They share the package-local Python backend and read only the generated installer projection under assets/installer/ plus the same-level bootstrap descriptor. Platform IDs, root resolution, target templates, status text, exit codes, transaction policy, and verification cases are data-driven by config/installer/; do not add platform branches or current test values to code or comments.
Install only from a versioned payload with the configured RELEASE_RECEIPT.json. Use --DryRun/--dry-run to validate without creating transaction resources; use replacement flags only when the target and overwrite intent are explicit. A transaction handles one platform and one target, preserves unlisted target files, writes an install receipt, and attempts rollback on failure. Unknown IDs and source directories without a valid release receipt fail closed. See references/skill/installation.md for the complete contract and parameterized invocation templates.
regular by default; use deep_review only when its extra review stage adds value; use agentic_repair only for existing RTL.Every module generated or modified by this skill must ship with a same-name <module>_spec.md companion. The canonical JSON contract accepts a single legacy module projection or a modules array, but each normalized module must declare a safe .v rtl_path, complete interface ports, clock/reset semantics, cycle behavior, constraints, corner cases, verification cases, and at least one timing_diagrams entry. A timing entry contains id, title, scenario, description, and WaveJSON with named signals. python -m scripts.python.workflow.cli write-spec --spec <spec.json> --out-dir <artifact-root> [--source <rtl.v>] --language <zh|en> writes spec/<feature>/<module>_spec.md plus sibling spec/<feature>/waveforms/<module>_<scenario>.json5 and .svg. The --source form fails closed when a module or port is undeclared; the no-source form validates and renders only the confirmed spec and never infers behavior from RTL. All waveform rendering goes through the renderer runtime declared by the settings authority and fails closed when its configured Node/npm prerequisites, package identity, version, or executable are unavailable. A render failure stages diagnostics without overwriting the previous valid bundle.
The default profile is erie_strict. Its authoritative naming, bilingual header, region, FSM, comment, port-order, runtime-message, and formatter-AST rules live in references/rules/verilog-code-comment-naming-standard.md, references/rules/erie-style.md, references/rules/verilog-comment-placement.md, and machine-readable assets. Do not duplicate those rule catalogs in this entry document.
Strict quality control is mandatory. ASIC quality review, independent static lint, and testbench scaffold are optional workflow steps selected only when the task needs their evidence. Optional helper tools are inside the workflow and never replace the generated-deliverable gate.
Generated deliverables must pass the formatter-backed gate with zero errors and zero strict warnings. The public result matrix is exactly compile, ast, readability, comment, naming, profile, testbench, and toolchain; static compile evidence does not imply that an external simulator, synthesis, or remote validation ran.
Verilog/SystemVerilog filenames must describe real function. Functional digits are valid; VG148 rejects only terminal version or meaningless numeric suffixes. A file recognized as a testbench by tb_, _tb, testbench, or an exact tb/testbench/sim directory must use the tb_<function>.v or tb_<function>.sv form; _tb is recognition evidence, not an allowed output name. When an ordinary design filename carries at least two independent testbench-content evidence groups, VG149 remains inconclusive until the user confirms design or testbench through file_role_confirmations. Confirming testbench does not waive the prefix rule: rename the file to the authority-selected tb_<function> form before it can pass. VG150 rejects configured workflow/evidence phrases on entity comments and high-confidence periodic unrelated tail families; it does not blacklist ordinary Chinese words or isolated functional descriptions. The full filename and comment contract lives in references/rules/verilog-code-comment-naming-standard.md, and gate/report semantics live in references/rules/verilog-quality-gates.md.
Use strict mode for new or modified deliverables. --non-strict --warn-only is limited to historical reference-corpus analysis and never approves generated output. The formatter backend under scripts/python/quality/formatter_backend/ is the parser source for quality checks; do not add a second Verilog parser.
For comment-only work, normalize the original RTL once, annotate a copy, run the comment-only verifier with a required delta, run the final gate, and compare the final file again against the immutable baseline. Comments must not change RTL tokens, modules, ports, lvalues, resets, always targets, or instance connections. Reused generic entity comments do not satisfy semantic-comment coverage.
When VG097 cannot see an external XPM, UNISIM primitive, or project-generated IP interface, first consult the exact-name AMD-Xilinx primitive catalog in assets/xilinx_primitive_semantics.json and its detailed contract in references/rules/xilinx-primitive-exemptions.md. Keep the result inconclusive until a governed pure-interface .v source is supplied through the repeatable --external-interface-source option when the name is not cataloged or the profile conflicts. Use the registered quality.external-interface-extract command for explicit vendor-source module whitelists and quality.external-interface-manifest for reviewed project-IP contracts. Never infer that an unknown width is a mismatch, and never use a stub or primitive profile as simulation, synthesis, implementation, or hardware evidence.
Generated RTL must remain synthesizable Verilog-2001. Prefer the governed interface templates for AXI-Stream, AXI4-Lite, AXI4, AHB, and APB; use complete combinational assignments and case defaults; avoid raw gated clocks; document CDC/reset assumptions; keep datapath and control timing-reviewable; and avoid generated function or task blocks when explicit logic is clearer for waveform debug. Every FSM must use three independent processes for the state register, procedural combinational next-state logic, and state output/task logic; a continuous assign to any next-state signal is forbidden. Every continuous or procedural combinational target must pass both the transitive source-cone limit and the configured real-operation budget, each defaulting to at most three. VG146/VG147 evaluate the complete source closure: formatter structured port associations bind child outputs into the parent cone, parameter/localparam specialization selects the materialized implementation, and each definition root, full instance path, specialization fingerprint, and static target remains an independent report identity. Output connections expand through known implementations; inout and unresolved-net boundaries never invent reverse ownership; all known wire/tri drivers are merged; and a clocked output Q cuts upstream expansion while its D input remains checked. The operation budget covers unary, binary, ternary, comparison, selector, control-decode, continuous-assign, combinational-process, clocked D-input, and elaborated for operations. Moving logic into always @(*) or directly into a clocked D expression does not bypass either gate. If loop_presence=unknown, VG146 and VG147 both apply and share the same lower-bound evidence: an over-limit known lower bound fails both, otherwise both remain inconclusive. When the operation budget fails, recommend pipeline registers, registered flags or predecode, or a multicycle FSM decomposition first, and disclose that these changes may alter visible latency; immutable-latency protocols require manual architecture review. Only an exact output bridge from an output port to a clocked internal _o reg is exempt from the source-cone rule. Detailed VG rules and ASIC review criteria remain authoritative in references/rules/verilog-quality-gates.md and references/rules/asic-verilog-quality.md.
VG151-VG155 provide module-independent structural contracts. Parameter constraints are selected automatically from the identifiers in each restricted expression; module, instance, hierarchy, and scope fields are invalid. VG152 reports large dynamically selected packed storage with a configurable positive threshold and offers structured case/FSM, inferred-memory, or vendor-memory alternatives. VG153/VG154 expose read-without-driver and unused declaration evidence, including reg/wire/function/task facts. VG155 uses explicit top-level ready-valid role facts and requires both valid and ready for a transfer consumer; no target module name is p
name: readable-verilog-generator description: >- Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis.
--- name: readable-verilog-generator description: >- Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis. --- # Readable Verilog Generator Generate, analyze, improve, and verify readable Verilog-2001 RTL through the bundled runtime under `scripts/python/`. Keep design RTL and verification testbenches in `.v` files, use `scripts/python/facade/verilog_api.py` for host integration, and treat formatter-AST and external-tool evidence as stronger than model self-assessment. ## Route - `create/write`: confirm the design contract, then use `requirements -> codegen_plan -> spec_document -> python -> rtl`. - `deep_review`: insert a non-empty structured review between the Python semantic model and RTL; it must cover interface, reset, timing/pipeline, handshake or FSM behavior, width, synthesis, testbench coverage, and risks. - `review/analyze`: remain read-only and report the eight public gate states before suggesting changes. - `annotate`: preserve an immutable normalized baseline, change only `//` comments, prove token equivalence from that baseline, and rerun the final deliverable gate. - `repair/refactor`: bind the task to real RTL, reproduce or validate the issue, and apply the smallest evidence-backed change. - `agentic_repair`: use the existing-RTL `verify_existing_verilog(...)` loop with an explicit `conservative`, `semi_auto`, or `auto_apply` choice. - `validate`: collect static or external evidence without implicitly editing RTL. - Load `references/workflows/verilog_dispatcher.md` before routing. Existing assets, logs, waveform clues, and mixed inputs use its read-only entry decision before any generation, validation, backup, or remote action. ## Install v2.0.0 The package root contains `install.ps1`, `install.sh`, and `install.bat` beside this `SKILL.md`. They share the package-local Python backend and read only the generated installer projection under `assets/installer/` plus the same-level bootstrap descriptor. Platform IDs, root resolution, target templates, status text, exit codes, transaction policy, and verification cases are data-driven by `config/installer/`; do not add platform branches or current test values to code or comments. Install only from a versioned payload with the configured `RELEASE_RECEIPT.json`. Use `--DryRun`/`--dry-run` to validate without creating transaction resources; use replacement flags only when the target and overwrite intent are explicit. A transaction handles one platform and one target, preserves unlisted target files, writes an install receipt, and attempts rollback on failure. Unknown IDs and source directories without a valid release receipt fail closed. See `references/skill/installation.md` for the complete contract and parameterized invocation templates. ## Generate And Modify 1. Confirm module name, ports, clock/reset, behavior, pipeline expectation, interface family, and verification cases. 2. Use `regular` by default; use `deep_review` only when its extra review stage adds value; use `agentic_repair` only for existing RTL. 3. Generate a Python semantic model before RTL in the staged workflow and use it as the testbench semantic contract. 4. Select local interface and ADC/DAC family templates only when the confirmed design matches them; record every adaptation in the requirements and codegen plan. 5. Keep batch execution generation-only, with one run directory per confirmed spec. Do not use batch mode for existing-RTL mutation or decision resume. 6. Treat streaming as provider interaction only. The finalized response artifact remains the extraction source of truth. 7. Run the strict generated-deliverable gate before downstream use. Optional lint and testbench helpers never replace it. Every module generated or modified by this skill must ship with a same-name `<module>_spec.md` companion. The canonical JSON contract accepts a single legacy module projection or a `modules` array, but each normalized module must declare a safe `.v` `rtl_path`, complete interface ports, clock/reset semantics, cycle behavior, constraints, corner cases, verification cases, and at least one `timing_diagrams` entry. A timing entry contains `id`, `title`, `scenario`, `description`, and WaveJSON with named signals. `python -m scripts.python.workflow.cli write-spec --spec <spec.json> --out-dir <artifact-root> [--source <rtl.v>] --language <zh|en>` writes `spec/<feature>/<module>_spec.md` plus sibling `spec/<feature>/waveforms/<module>_<scenario>.json5` and `.svg`. The `--source` form fails closed when a module or port is undeclared; the no-source form validates and renders only the confirmed spec and never infers behavior from RTL. All waveform rendering goes through the renderer runtime declared by the settings authority and fails closed when its configured Node/npm prerequisites, package identity, version, or executable are unavailable. A render failure stages diagnostics without overwriting the previous valid bundle. The default profile is `erie_strict`. Its authoritative naming, bilingual header, region, FSM, comment, port-order, runtime-message, and formatter-AST rules live in `references/rules/verilog-code-comment-naming-standard.md`, `references/rules/erie-style.md`, `references/rules/verilog-comment-placement.md`, and machine-readable assets. Do not duplicate those rule catalogs in this entry document. ## Quality Strict quality control is mandatory. ASIC quality review, independent static lint, and testbench scaffold are optional workflow steps selected only when the task needs their evidence. Optional helper tools are inside the workflow and never replace the generated-deliverable gate. Generated deliverables must pass the formatter-backed gate with zero errors and zero strict warnings. The public result matrix is exactly `compile`, `ast`, `readability`, `comment`, `naming`, `profile`, `testbench`, and `toolchain`; static compile evidence does not imply that an external simulator, synthesis, or remote validation ran. Verilog/SystemVerilog filenames must describe real function. Functional digits are valid; VG148 rejects only terminal version or meaningless numeric suffixes. A file recognized as a testbench by `tb_`, `_tb`, `testbench`, or an exact `tb`/`testbench`/`sim` directory must use the `tb_<function>.v` or `tb_<function>.sv` form; `_tb` is recognition evidence, not an allowed output name. When an ordinary design filename carries at least two independent testbench-content evidence groups, VG149 remains inconclusive until the user confirms `design` or `testbench` through `file_role_confirmations`. Confirming `testbench` does not waive the prefix rule: rename the file to the authority-selected `tb_<function>` form before it can pass. VG150 rejects configured workflow/evidence phrases on entity comments and high-confidence periodic unrelated tail families; it does not blacklist ordinary Chinese words or isolated functional descriptions. The full filename and comment contract lives in `references/rules/verilog-code-comment-naming-standard.md`, and gate/report semantics live in `references/rules/verilog-quality-gates.md`. Use strict mode for new or modified deliverables. `--non-strict --warn-only` is limited to historical reference-corpus analysis and never approves generated output. The formatter backend under `scripts/python/quality/formatter_backend/` is the parser source for quality checks; do not add a second Verilog parser. For comment-only work, normalize the original RTL once, annotate a copy, run the comment-only verifier with a required delta, run the final gate, and compare the final file again against the immutable baseline. Comments must not change RTL tokens, modules, ports, lvalues, resets, always targets, or instance connections. Reused generic entity comments do not satisfy semantic-comment coverage. When `VG097` cannot see an external XPM, UNISIM primitive, or project-generated IP interface, first consult the exact-name AMD-Xilinx primitive catalog in `assets/xilinx_primitive_semantics.json` and its detailed contract in `references/rules/xilinx-primitive-exemptions.md`. Keep the result `inconclusive` until a governed pure-interface `.v` source is supplied through the repeatable `--external-interface-source` option when the name is not cataloged or the profile conflicts. Use the registered `quality.external-interface-extract` command for explicit vendor-source module whitelists and `quality.external-interface-manifest` for reviewed project-IP contracts. Never infer that an unknown width is a mismatch, and never use a stub or primitive profile as simulation, synthesis, implementation, or hardware evidence. Generated RTL must remain synthesizable Verilog-2001. Prefer the governed interface templates for AXI-Stream, AXI4-Lite, AXI4, AHB, and APB; use complete combinational assignments and case defaults; avoid raw gated clocks; document CDC/reset assumptions; keep datapath and control timing-reviewable; and avoid generated `function` or `task` blocks when explicit logic is clearer for waveform debug. Every FSM must use three independent processes for the state register, procedural combinational next-state logic, and state output/task logic; a continuous `assign` to any next-state signal is forbidden. Every continuous or procedural combinational target must pass both the transitive source-cone limit and the configured real-operation budget, each defaulting to at most three. VG146/VG147 evaluate the complete source closure: formatter structured port associations bind child outputs into the parent cone, parameter/localparam specialization selects the materialized implementation, and each definition root, full instance path, specialization fingerprint, and static target remains an independent report identity. Output connections expand through known implementations; inout and unresolved-net boundaries never invent reverse ownership; all known wire/tri drivers are merged; and a clocked output Q cuts upstream expansion while its D input remains checked. The operation budget covers unary, binary, ternary, comparison, selector, control-decode, continuous-assign, combinational-process, clocked D-input, and elaborated `for` operations. Moving logic into `always @(*)` or directly into a clocked D expression does not bypass either gate. If `loop_presence=unknown`, VG146 and VG147 both apply and share the same lower-bound evidence: an over-limit known lower bound fails both, otherwise both remain inconclusive. When the operation budget fails, recommend pipeline registers, registered flags or predecode, or a multicycle FSM decomposition first, and disclose that these changes may alter visible latency; immutable-latency protocols require manual architecture review. Only an exact output bridge from an output port to a clocked internal `_o` `reg` is exempt from the source-cone rule. Detailed VG rules and ASIC review criteria remain authoritative in `references/rules/verilog-quality-gates.md` and `references/rules/asic-verilog-quality.md`. VG151-VG155 provide module-independent structural contracts. Parameter constraints are selected automatically from the identifiers in each restricted expression; `module`, `instance`, `hierarchy`, and `scope` fields are invalid. VG152 reports large dynamically selected packed storage with a configurable positive threshold and offers structured case/FSM, inferred-memory, or vendor-memory alternatives. VG153/VG154 expose read-without-driver and unused declaration evidence, including reg/wire/function/task facts. VG155 uses explicit top-level ready-valid role facts and requires both valid and ready for a transfer consumer; no target module name is p
Skill source recorded
Skill instructions are recorded. This is not a runtime test, safety guarantee or compatibility certification.
Review before install: Avoid automatic install
License: Apache-2.0
Repository metadata and review signals are advisory. Popularity, source discovery and successful execution are different facts.
Version reported in registry metadata; check source releases before relying on it.
Quality
71/100
Strong
Trust
58/100
Do not auto-install
This page exposes the same decision, trust, audit, use-case, and install signals through the Registry API, so agents can rank this skill without scraping the UI.
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"score": 71,
"label": "Strong"
},
"supply": {
"track": "Data, BI, and analytics",
"scenario": "Browser automation",
"maintenance": "23d since push",
"risk": "Needs review"
},
"alternative_skills": [],
"do_not_use_when": [
"teams that need a vendor-supported SLA",
"production agents without a repository review",
"SKILL.md excerpt is truncated in the review, but the provided content is clear and complete enough to assess.",
"High-risk permission hints: Shell or command execution, Secrets or environment access",
"Dependency or permission surface needs review",
"Permission surface may require sandboxing",
"Financial research output is not financial advice; require human review before any live investment decision",
"The skill relies on external tools like Vivado/xsim for validation, which may not be available in all environments, but this is a functional limitation rather than a security concern."
],
"agent_contract": {
"task_input": "Use readable-verilog-generator in an agent workflow",
"recommended_action": "Do not auto-install. Inspect the source, dependencies, and permission surface first.",
"install_policy": "block",
"minimum_review_before_use": [
"Trust: 66/100 Manual review",
"Audit: 76/100 Needs review",
"Safety: 32/100 Avoid automatic install",
"Review repository, license, install command, and permission surface before production use."
],
"expected_agent_output": {
"selected_skill": "eriemon-readable-verilog-generator (readable-verilog-generator)",
"install_command": "npx skills add Eriemon/verilog-generator --skill readable-verilog-generator",
"risk_summary": "Needs review; Blocked for auto-install; Review before production",
"verification_result": "Report the smallest successful task, files touched, warnings, and any missing setup."
}
},
"outcome_feedback": {
"endpoint": "https://www.openagentskill.com/api/agent/outcome",
"method": "POST",
"requires_resolve_event_id": true,
"event_id_source": "Use install_receipt.outcome_feedback.event_id or feedback.event_id returned by /api/agent/resolve for the current task.",
"expected_outcomes": [
"success",
"failed",
"not_relevant",
"blocked_by_risk",
"setup_required"
],
"payload_template": {
"event_id": "<install_receipt.outcome_feedback.event_id or feedback.event_id from /api/agent/resolve>",
"skill_slug": "eriemon-readable-verilog-generator",
"task": "Use readable-verilog-generator in an agent workflow",
"agent": "codex",
"outcome": "success",
"install_used": true,
"risk_blocked": false,
"setup_required": false,
"task_success": true,
"output_quality": 4,
"error_type": null,
"human_review_required": false,
"workspace": "sandbox",
"time_to_useful_ms": 120000,
"notes": "Report the smallest successful task, setup friction, files touched, and risk notes."
}
},
"endpoints": {
"web": "https://www.openagentskill.com/skills/eriemon-readable-verilog-generator",
"api": "https://www.openagentskill.com/api/agent/skills/eriemon-readable-verilog-generator",
"audit": "https://www.openagentskill.com/skills/eriemon-readable-verilog-generator/audit",
"eval": "https://www.openagentskill.com/api/agent/evals?slug=eriemon-readable-verilog-generator&task=Use%20readable-verilog-generator%20in%20an%20agent%20workflow&max_risk=medium",
"resolve": "https://www.openagentskill.com/api/agent/resolve?task=Use%20readable-verilog-generator%20in%20an%20agent%20workflow&agent=codex&max_risk=medium",
"receipt": "https://www.openagentskill.com/api/agent/receipt?task=Use%20readable-verilog-generator%20in%20an%20agent%20workflow&agent=codex&max_risk=medium&format=text",
"install": "https://www.openagentskill.com/api/skills/eriemon-readable-verilog-generator/install",
"manifest": "https://www.openagentskill.com/api/registry/manifest/eriemon-readable-verilog-generator"
}
}Listing source
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Audit
76/100
Needs review
Copies are not installs. Installation counts require a reported successful installation; they are not a blanket quality guarantee.